1. Field of the Invention
This invention relates generally to frequency synthesizers, and in particular to fractional frequency synthesizers.
2. Related Art
A diagram of a conventional phase-locked loop (PLL) synthesizer 100 is shown in FIG. 1. The conventional PLL contains a fixed integer divider 102, whose modulus N provides a fixed relation between the external reference frequency fREF 104 and the internal voltage-controlled oscillator (VCO) 106 frequency fVCO. The output of the integer divider 102 is compared to the reference frequency 104 by the phase-frequency detector (PAD) 108. The PAD 108 produces an error signal, which is proportional to the phase error between the reference frequency 104 and the integer divider 102 output. This error signal is filtered by loop filter 110 and applied to the VCO 106 input, which increases or decreases the VCO frequency until the PLL is locked. Once locked, the VCO frequency is given by: fVCO=fREF*N. Thus, with a conventional PLL only a single reference frequency can be used for a given design, and that reference frequency must be an integer multiple of the desired VCO frequency. This places limitations on application and design.
Fractional synthesizers enable the synthesis of a VCO frequency which is not an integer multiple of the reference frequency. In a fractional-N type synthesizer a variable integer frequency divider, having an integer divide value “n” is used, where “n” can be switched between different integer values in integer steps. A modulator is used to vary the modulus “n” of the variable integer frequency divider.
A diagram of a fractional-N synthesizer 200 is shown in FIG. 2. In the fractional-N synthesizer, the instantaneous relation between the output of variable integer divider 204 and frequencies generated by the VCO 106 is given by fDIV=fVCO/n, where n=. . . , N−1, N, N+1, . . . . By the modulator 202 dynamically varying n used by the variable integer divider 204 between the different integer values, fractional values of n may be synthesized, when averaged over many cycles. The modulator is clocked by the output of divider 204. The range over which “n” is dynamically varied depends on the type and order of the modulator 202. Furthermore, by having more module in the integer divider 102 than are needed for the fractional synthesis, the value “N” around which the dynamic modulation takes place, can be set to different integer values for different frequency plans.
This is illustrated in the fractional-N synthesizer 300 by the “integer set” input in FIG. 3. Thus, a large range of reference frequencies 104 can be used for a given fractional-N synthesizer design. The flexibility of fractional-N synthesis does result in some degradation of synthesizer performance, compared to a conventional PLL 100. The dynamic modulation is perpetually pulling the loop away from an ideal locked condition, and the loop is perpetually compensating for this by sending error signals to the VCO. This perpetual perturbation of the PLL causes excess phase noise in the spectrum of the VCO Output.
Most known fractional-N synthesizers use sigma-delta (ΣΔ) modulators 304 to control the modulus of the variable divider 302. The ΣΔ modulators 304 used in fractional-N synthesizers are purely digital circuits that produce one or more patterns of 1's and 0's as their output. The periodicity and frequency content of the digital patterns produced will determine the spectral quality of the synthesizer output. ΣΔ modulators 304 consist of one of more digital integrators or accumulators. Higher order modulators (with two or more integrators) shape the noise added to the VCO 106 spectrum, by pushing the quantitation noise to higher frequencies, where the loop filter 110 of the PLL can more easily filter it. The type and order of the ΣΔ modulator 304 determines the exact shape of the noise shaping function, and has a direct impact on the noise in output spectrum of the synthesizer.
There are two types of ΣΔ modulators commonly used in fractional-N synthesizers:
(1) Cascade or MASH Modulators: This topology is a cascade of two or more integrators or accumulators. The output of one accumulator is the input of the following. There are feed-forward paths from the overflow outputs of each accumulator to the final output, but there are no feedback paths external to the accumulators. Having no feedback is what distinguishes MASH modulators from the other types of ΣΔ modulators. It is also this property that gives MASH modulators the advantage of being unconditionally stable. MASH modulators are easy to design and implement and produce compact designs. The disadvantages of MASH modulators include: 1) the noise shaping function depends only on the order of the modular (which is equal to the number of integrators), and cannot optimized for the PLL; 2) MASH modulators always have multi-bit outputs which require multi-modulus dividers.
(2) Feedback Modulators: Feedback modulators have one or more feedback paths external to the integrators. There is usually at least one feedback path from output to the input. Feedback modulators may also have one or more feed-forward paths. As with MASH modulators, the number of integrators determines the order of the modulator. Unlike the MASH modulator there is more flexibility in the design by the choice of the feedback and forward paths and the coefficients of the feedback and feed-forward paths. Although the control of the noise shaping function is desirable, it also makes designs more complicated. Unlike the MASH modulator the feedback modulator is NOT unconditionally stable and requires careful choice of the feedback and feed-forward paths and coefficients to ensure stability. The feedback modulator may have a single bit output, which only requires a dual modulus divider, however multi-bit outputs are often used to improve the noise shaping. A generalized description of feedback type modulators is provided in reference: K. Chaos et. al, “A higher order topology for interpolative modulators for over sampling A/D converters”, IEEE Transactions on Circuits and Systems, vol. 37, No. 3, pp. 309-318, March 1990.
U.S. Pat. No. 5,038,117, which is incorporated by reference herein, describes a fractional-N type synthesizer, using cascade or MASH type ΣΔ modulator. A third order MASH modulator is described and the generalized application of this method is illustrated for an Mth order MASH modulator. In this architecture the number of control bits applied to the input of the divider are equal to the order of the modulator. Thus, for a 3rd order modulator, the modulus of the divider varies dynamically between eight states: N−3, N−2, N−1, N, N+1, N+2, N+3, and N+4, where N is the nominal divide ratio. This represents significant perturbation of the PLL.
Thus, there is a need in the art for a fractional-R synthesizer that can be switched in rational values that eliminate the limitations of known fractional-N type synthesizers.